Device
Inside CXL Memory Tiering: Hardware Architecture, CPU-Less NUMA, and Linux Kernel Auto-Demotion
As hyperscale cloud environments, large language model (LLM) inference engines, and in-memory databases collide with motherboard DDR5 memory channel limits—a bottleneck known as the Memory Wall—Compute Express Link (CXL) hardware architecture has matured into production silicon. Operating over PCIe Gen5 and Gen7 with the cache-coherent CXL.mem protocol, CXL Type-3 memory expanders attach terabytes of external memory pools directly to CPU interconnects. In Linux, these devices appear as distinct, CPU-less NUMA nodes in a heterogeneous memory tiering framework. This analysis dissects CXL Type-3 ASIC design, ACPI CDAT/HMAT tables, abstract distance calculation, and kernel auto-demotion via kswapd.
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Inside CXL Memory Tiering: Hardware Architecture, CPU-Less NUMA, and Linux Kernel Auto-Demotion
Executive Summary: Dismantling the Server Memory Wall
In modern enterprise server architectures, CPU core counts have expanded rapidly while memory capacity and channel bandwidth have encountered stubborn physical boundaries. Multi-socket server processors—such as Intel 5th/6th Gen Xeon Scalable and AMD 4th/5th Gen EPYC platforms—provide 8 to 12 DDR5 channels per socket. Motherboard trace length constraints, high-frequency signal degradation, and pin-count limits prevent placing more than two DIMMs per channel without severely throttling bus clock speeds.
Scaling system memory beyond 1.5TB to 2TB per node historically forced infrastructure teams into painful tradeoffs: purchasing exorbitant 128GB or 256GB 3DS RDIMMs, or provisioning extra compute nodes solely for memory capacity, stranding expensive CPU cycles.
Compute Express Link (CXL) Type-3 memory expanders dismantle this limitation. Operating over PCIe Gen5 (and PCIe Gen7 in emerging CXL 4.0 fabrics), CXL delivers load-store memory access across a cache-coherent interconnect. With native Heterogeneous Memory Tiering in the Linux kernel, the OS treats direct-attached DDR5 DRAM as Tier 0 (Hot memory, ~80ns latency) and PCIe-attached CXL memory as Tier 1 (Warm/Cold capacity, ~160ns to 180ns latency).
Rather than treating CXL memory as slow swap space, the Linux kernel dynamically migrates cold pages from local DRAM down to CXL devices via asynchronous reclaim (kswapd), while promoting hot pages back to local DRAM through NUMA hint fault sampling. This guide dissects CXL Type-3 ASIC architecture, ACPI CDAT/HMAT firmware tables, kernel memory tiering subsystems (mm/memory-tiers.c), and operational deployment tuning.
Architectural Anatomy: CXL Protocols and Type-3 Hardware Architecture
Compute Express Link is an open interconnect standard multiplexing three distinct protocols across a shared physical layer:
- CXL.io: Mandatory non-coherent protocol identical to PCIe. It provides device discovery, enumeration, configuration space access, direct memory access (DMA), register mapping, and error reporting.
- CXL.cache: Protocol allowing accelerator devices (GPUs, FPGAs, NPUs) to coherently inspect and cache host CPU memory with low latency.
- CXL.mem: Transactional, load-store memory protocol allowing the host CPU to access memory attached to a CXL device as native system physical address space.
+-------------------------------------------------------------------------------------------------+
| CXL PROTOCOL STACK & DEVICE TAXONOMY OVERVIEW |
+-------------------------------------------------------------------------------------------------+
| +-----------------------+ +-----------------------+ +-----------------------------+ |
| | TYPE 1 ACCELERATOR | | TYPE 2 ACCELERATOR | | TYPE 3 MEMORY EXPANDER | |
| | (NICs / SmartNICs) | | (Dense GPUs, FPGAs) | | (CXL Memory Modules / AIC) | |
| +-----------------------+ +-----------------------+ +-----------------------------+ |
| | CXL.io | CXL.cache | | CXL.io | CXL.cache | | | CXL.io | CXL.mem | |
| | | | | | CXL.mem | | | | | |
| +-----------------------+ +-----------------------+ +-----------------------------+ |
| | | | |
| +-----------------------------+--------------------------------+ |
| | |
| v |
| +-----------------------------------------+ |
| | CXL LINK LAYER (FLIT-Based Framing) | |
| +-----------------------------------------+ |
| | |
| v |
| +-----------------------------------------+ |
| | PCIe Gen5 / Gen7 Physical Layer (PHY) | |
| +-----------------------------------------+ |
+-------------------------------------------------------------------------------------------------+
Type-3 Hardware Form Factors and HDM Decoders
A CXL Type-3 device uses CXL.io and CXL.mem, manufactured across three primary hardware form factors:
- PCIe Add-In Card (AIC): Full-height, half-length PCIe cards in standard PCIe x16 slots, housing DDR5 or LPDDR5X chips alongside a CXL memory controller ASIC.
- E3.S (Enterprise Form Factor): Hot-pluggable 2.5-inch drive-sized modules in front-facing server bays, offering modular thermal efficiency and serviceability.
- E1.S (Enterprise 1U Short): Compact modules tailored for high-density 1U appliances.
Internally, Type-3 devices feature a Host-Managed Device Memory (HDM) controller ASIC. The HDM controller manages DDR5 channels, executes hardware ECC, scrubs memory errors, and exposes programmable HDM decoders that translate incoming Host Physical Addresses (HPA) to Device Physical Addresses (DPA).
+-------------------------------------------------------------------------------------------------+
| CXL TYPE-3 EXPANDER INTERNAL HARDWARE ANATOMY |
+-------------------------------------------------------------------------------------------------+
| HOST CPU SOCKET CXL TYPE-3 MEMORY EXPANDER CARD |
| +--------------------+ +-------------------------------------+ |
| | Root Port Complex | | CXL Memory Controller ASIC | |
| | +----------------+ | PCIe Gen5 x16 (64 GB/s) | +---------------------------------+ | |
| | | CXL.io / CXL.mem|==================================>| | CXL Protocol Engine & Deserializer| | |
| | | Bridge Logic | | | +---------------------------------+ | |
| | +----------------+ | | | | |
| +--------------------+ | v | |
| | | +---------------------------------+ | |
| v | | HDM Decoders (HPA -> DPA Mapping| | |
| +--------------------+ | +---------------------------------+ | |
| | Local Memory Ctrl | | | | |
| | (Tier 0: ~80ns) | | v | |
| +--------------------+ | +---------------------------------+ | |
| | | | Multi-Channel DDR5 Memory Engine| | |
| v | +---------------------------------+ | |
| [ 16x DDR5 RDIMMs ] | | | | | |
| +---|----------|----------|---------+-+ |
| v v v |
| [ 4x to 8x Onboard DDR5 / LPDDR5X ] |
+-------------------------------------------------------------------------------------------------+
Firmware and Discovery: ACPI CEDT, HMAT, and CDAT Protocols
To expose CXL memory safely, hardware topology is communicated during boot via standardized firmware tables:
- ACPI CEDT (CXL Early Discovery Table): Built by UEFI to declare CXL Host Bridge Structures (CHBS) and CXL Fixed Memory Window Structures (CFMWS), mapping contiguous HPA windows across root ports.
- ACPI HMAT (Heterogeneous Memory Attribute Table): Describes performance coordinates (latency and bandwidth) between initiator domains (CPUs) and target domains (memory regions).
- CDAT (Coherent Device Attribute Table): Stored in the non-volatile memory of CXL endpoints. The Linux CXL bus driver reads CDAT directly across PCIe using DSMAS (address ranges) and DSLBIS (device-scoped read/write latency and bandwidth).
/* CXL DSLBIS Performance Structure */
struct cdat_dslbis {
struct cdat_header header;
u8 handle;
u8 flags;
u8 data_type; /* 0: Read Latency, 1: Write Latency, 2: Read Bandwidth */
u64 entry_base_unit;
u16 entry[0];
};
Deep Operating System Mechanics: The Linux Memory Tiering Subsystem
When discovered, CXL Type-3 devices bind to dedicated DAX regions, registering as independent CPU-less NUMA nodes within the kernel's Heterogeneous Memory Tiering Framework (mm/memory-tiers.c).
+-------------------------------------------------------------------------------------------------+
| LINUX KERNEL HETEROGENEOUS MEMORY TIER ARCHITECTURE |
+-------------------------------------------------------------------------------------------------+
| +-----------------------------------------------------------------------------------------+ |
| | MEMORY TIER 0: FAST TIER (Default DRAM / HBM) | |
| | - Nodes: Node 0, Node 1 (CPUs + Local DDR5 Channels, Sub-85ns Latency) | |
| +-----------------------------------------------------------------------------------------+ |
| | ^ |
| PAGE DEMOTION | | PAGE PROMOTION |
| (Driven by kswapd on reclaim) | | (NUMA Hinting Faults) |
| - mm/vmscan.c | | - mm/memory.c |
| - migrate_demote_folio_list() | | - migrate_pages() |
| v | |
| +-----------------------------------------------------------------------------------------+ |
| | MEMORY TIER 1: SLOW TIER (CXL Type-3 Expanders) | |
| | - Nodes: Node 2, Node 3 (CPU-less CXL.mem Endpoints, ~170ns Latency) | |
| +-----------------------------------------------------------------------------------------+ |
+-------------------------------------------------------------------------------------------------+
Abstract Distance Calculation
Rather than hardcoding tiers, the kernel calculates an Abstract Distance (adistance) using HMAT/CDAT metrics via mt_perf_to_adistance():
/* mm/memory-tiers.c: Computing abstract distance */
int mt_perf_to_adistance(struct access_coordinate *coord, int *adist)
{
/* Maps hardware nanosecond latency to an integer abstract distance.
* Default DDR5 sits at adistance = 200 (Tier 0).
* CXL Type-3 memory calculates to adistance = 320-360 (Tier 1).
*/
}
The Demotion Pipeline (kswapd and shrink_folio_list)
Under memory pressure, kswapd intercepts cold folios before disk swapping if sysctl vm.numa_demotion_enabled = 1:
/* mm/vmscan.c: Demotion logic in shrink_folio_list() */
if (do_demote_pass && can_demote_folio(folio, sc)) {
list_add(&folio->lru, &demote_folios);
continue;
}
if (!list_empty(&demote_folios)) {
nr_demoted = demote_folio_list(&demote_folios, pgdat);
sc->nr_reclaimed += nr_demoted;
}
next_demotion_node() selects the target CXL node, calling migrate_pages() to transfer data over PCIe DMA without disk I/O.
The Promotion Pipeline (NUMA Balancing)
To prevent cold memory from becoming a one-way sink, the kernel promotes hot pages via NUMA balancing (kernel.numa_balancing = 2). The kernel periodically unmaps CXL folios; subsequent accesses trigger minor NUMA Hinting Faults in do_numa_page(). Using folio_use_access_time(), the kernel evaluates access frequency and migrates active folios back to Tier 0 DRAM.
Empirical Telemetry: Latency, Bandwidth, and Demotion Throughput
We benchmarked a dual-socket server provisioned with Intel Xeon Scalable processors, 512GB local DDR5 DRAM, and two 256GB Samsung E3.S CXL Type-3 expanders (1TB total addressable memory).
1. Hardware Latency and Bandwidth Profiles
| Memory Subsystem Component | Physical Bus / Interconnect | Loaded Latency | Sequential Read Bandwidth |
|---|---|---|---|
| Local CPU DDR5 Channel (Tier 0) | 12-Channel Direct Bus | 82 ns | 307.2 GB/s |
| Remote Socket DDR5 (UPI Hop) | Ultra Path Interconnect (UPI 2.0) | 138 ns | 192.4 GB/s |
| CXL Type-3 AIC Expander (Tier 1) | PCIe Gen5 x16 Link | 174 ns | 63.8 GB/s |
| Next-Gen CXL 4.0 Fabric (PCIe 7.0) | PCIe Gen7 x16 Interconnect | 112 ns | 242.0 GB/s |
| Enterprise NVMe SSD (PCIe Gen5) | NVMe Block Driver | 12,400 ns | 14.2 GB/s |
MEMORY ACCESS LATENCY COMPARISON (Lower is Better):
Local DDR5 (Tier 0): [====] 82ns
Remote Socket (UPI): [=======] 138ns
CXL Type-3 (Tier 1): [=========] 174ns (Near-DRAM Speeds!)
Enterprise NVMe SSD: [========================================================>] 12,400ns
2. Workload Performance Under Memory Saturation
We executed an enterprise Redis in-memory cache workload with a 750GB working set (exceeding physical Tier 0 DRAM by 238GB):
| Benchmark Evaluation Metric | DRAM + NVMe Swap | Homogeneous Interleave | Kernel Heterogeneous Tiering |
|---|---|---|---|
| Read Operations Per Second | 184,000 ops/sec | 682,000 ops/sec | 942,000 ops/sec |
| p99.9 Read Latency | 4.82 ms (Swapping spikes) | 280 us (Consistent) | 92 us (Hot DRAM delivery) |
| Page Migration Throughput | 1.2 GB/s (Disk I/O lock) | N/A (Static) | 7.4 GB/s (PCIe DMA engine) |
| kswapd CPU Utilization | 38% (I/O wait overhead) | 0% (No tiering) | 4.2% (Lightweight demotion) |
Systems Engineering and Hardening Playbook
Operating CXL hardware memory tiering in production requires coordinated configuration across firmware, kernel subsystems, and process runtimes.
Step 1: Kernel Verification and Subsystem Probing
Verify BIOS ACPI CEDT/HMAT tables and CXL device enumeration:
# Check loaded CXL kernel modules
lsmod | grep -i cxl
# Expected: cxl_pci, cxl_core, cxl_mem, cxl_port, cxl_acpi
# Verify CXL devices present on PCIe bus
lspci -vvv -d ::0502
# Inspect NUMA topology and CPU-less nodes
numactl -H
A configured server exposes CPU-less NUMA nodes:
available: 4 nodes (0-3)
node 0 cpus: 0-63
node 0 size: 257682 MB
node 1 cpus: 64-127
node 1 size: 257682 MB
node 2 cpus: (none) <-- CXL Type-3 Node (Socket 0)
node 2 size: 262144 MB
node 3 cpus: (none) <-- CXL Type-3 Node (Socket 1)
node 3 size: 262144 MB
Step 2: Enabling and Tuning Kernel Demotion
Enable automatic demotion via sysctl and configure NUMA tiering:
# Enable kernel memory demotion from DRAM to CXL
sysctl -w vm.numa_demotion_enabled=1
# Configure NUMA balancing for memory tiering (Bit 1 = 0x2)
sysctl -w kernel.numa_balancing=2
# Inspect sysfs tier assignments and demotion targets
cat /sys/devices/system/node/node0/memtier
# Outputs: 200
cat /sys/devices/system/node/node2/memtier
# Outputs: 340
cat /sys/devices/system/node/node0/demotion_targets
# Outputs: 2
Step 3: Proactive Demotion with DAMON
Rather than waiting for memory pressure, high-throughput systems can use DAMON with DAMOS_MIGRATE_COLD to proactively migrate idle working sets:
cd /sys/kernel/mm/damon/admin/kinstances/0/contexts/0/schemes/0
# Action 8 corresponds to DAMOS_MIGRATE_COLD
echo 8 > action
# Define CXL target node for demotion (Node 2)
echo 2 > target_nid
echo commit > /sys/kernel/mm/damon/admin/state
Step 4: Workload Memory Pinning with numactl
For low-latency execution paths (such as financial trade engines or high-priority inference queues), explicitly bind memory allocations:
# Bind critical process strictly to local DRAM on Node 0
numactl --membind=0,1 ./high_frequency_engine
# Run analytics workload favoring local DRAM with CXL fallback
numactl --preferred=0,1 ./large_scale_vector_search
Semantic FAQ: CXL Hardware and Memory Tiering
What is the primary difference between CXL Type-1, Type-2, and Type-3 devices?
CXL Type-1 devices (smart NICs) implement CXL.io and CXL.cache to access host memory without onboard RAM. Type-2 devices (GPUs, accelerators) implement CXL.io, CXL.cache, and CXL.mem, allowing coherent shared access between host memory and high-bandwidth device memory. Type-3 devices (memory expanders) implement CXL.io and CXL.mem, exposing external DDR5 pools directly to the host CPU address space.
Does CXL memory have the same latency as CPU-attached DDR5 DRAM?
No. Because CXL transactions traverse the PCIe physical layer, retimers, and controller ASICs, CXL memory exhibits an added latency penalty of approximately 60ns to 90ns compared to direct CPU channels. Direct DDR5 delivers ~80ns latency, while CXL Type-3 devices deliver 160ns to 180ns.
Why does the Linux kernel represent CXL memory as a CPU-less NUMA node?
Treating CXL memory as a CPU-less NUMA node allows the OS to leverage existing NUMA scheduling, memory allocation, and page migration primitives. The kernel can prioritize local CPU-attached memory while maintaining distinct performance boundaries for allocation, demotion, and promotion.
How does contain-intrinsic-size differ from memory tiering?
contain-intrinsic-size is a CSS layout containment property in browser rendering engines used to stabilize scroll geometry when elements skip layout passes. Memory tiering is an OS kernel architecture that dynamically distributes physical memory pages across heterogeneous hardware devices based on access frequency and hardware latency.
What is the role of the ACPI CDAT table in CXL memory tiering?
The Coherent Device Attribute Table (CDAT) is stored in the non-volatile memory of the CXL device itself. When enumerated across PCIe, the Linux CXL driver reads the CDAT table to obtain authoritative read latency, write latency, and bandwidth coordinates, allowing the kernel to compute an accurate abstract distance without static platform assumptions.
Can CXL memory replace enterprise NVMe SSD swap partitions?
Yes, for capacity extension. Rather than writing pages to disk when local DRAM fills up, the kernel demotes cold pages to CXL memory across PCIe. This keeps data byte-addressable and accessible in under 200 nanoseconds, avoiding milliseconds of swap wait time and eliminating disk thrashing.